1. Field of the Invention
This disclosure generally relates to circuits and techniques for communicating data from a transmitter to a receiver. More specifically, this disclosure relates to circuits and techniques that allow data from one clock domain to be safely captured in another clock domain, wherein the two clock domains have the same clock frequency, but an unknown phase offset.
2. Related Art
To simplify the designs of complex integrated circuits such as system-on-chip (SoC) or processors, circuit designers typically partition large circuits into several smaller circuits such that each has its own “clock domain.” Often, all of these clock domains receive their clock signals from a common clock source so that the clock frequency is the same for these different clock domains. However, because distribution delays of the common clock signal to various clock domains vary from one domain to another domain, the phase difference between different clock domains can be significant and difficult to determine. Consequently, efficient interface circuits that can compensate for such clock skews have to be provided between different clock domains so that data can be transferred reliably between these different clock domains. Some existing systems make use of first-in-first-out (FIFO) buffers to transfer data between different clock domains. However, FIFO buffers are complicated to implement and can introduce additional delay in data transfer between the different clock domains.
Other existing techniques provide an interface latch, and an associated latch control circuit between two clock domains for allowing data to cross from one clock domain to another. These techniques rely on the fact that there are two valid timing windows where the interface latch should receive the control signal from the latch control circuit in order to safely transfer data from one clock domain to another. During circuit initialization, the existing techniques continuously adjust a variable delay circuit in an attempt to locate the larger of the two valid timing windows. However, these existing techniques require both a complex initialization routine and latch control logic that uses functions implemented through dynamic CMOS circuits or C-elements that are not available in typical cell libraries.
Hence, what is needed is a circuit and technique that facilitate reliable data transfer between different clock domains without the above-described problems.